The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
As semiconductor technologies evolve, three-dimensional integrated circuit devices have emerged as an effective alternative to further reduce the physical size of a semiconductor chip. In a three-dimensional integrated circuit, the packaging is generated on the die with contacts provided by a variety of bumps. Much higher density can be achieved by employing three-dimensional integrated circuit devices. Furthermore, three-dimensional integrated circuit devices can achieve smaller form factors, cost-effectiveness, increased performance and lower power consumption.
In a three-dimensional integrated circuit, a first semiconductor die may be bonded on a second semiconductor die or a package substrate through a plurality of bumps and metal traces. In particular, a plurality of bumps may be formed on the top surface of the first semiconductor die. There may be a solder ball formed over each bump. The metal traces may be formed on the top surface of the second semiconductor die or the package substrate. The first semiconductor die may be flipped and attached to the second semiconductor die (or the package substrate) through a mating process between the bumps and their corresponding metal traces. Subsequently, a reflow process may be employed to melt the solder balls so that the bumps of the first semiconductor die and the metal traces of the second semiconductor die (or the package substrate) may form a plurality of bump-on-trace (BOT) structures. Such BOT structures help to bond two semiconductor dies (or a semiconductor die and a package substrate) together to form a three-dimensional integrated circuit.
The three-dimensional integrated circuit technology has a variety of advantages. One advantageous feature of packaging multiple semiconductor dies at the wafer level is multi-chip wafer level package techniques may reduce fabrication costs.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.